library verilog;
use verilog.vl_types.all;
entity led8 is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        regular         : in     vl_logic;
        random          : in     vl_logic;
        led8s           : out    vl_logic_vector(9 downto 0);
        led10s          : out    vl_logic_vector(9 downto 0)
    );
end led8;
